Posts about Verilog
I guess one of the important lessons I've learnt recently is how to read/understand someone else's code with little to no documentation. Eg: I know what the code I'm looking at is supposed to do at a very high level , but there are too many nets that I just don't understand - interfaces to packages, AXI pipelines, more stuff.
My method (which I'm finding is very ineffective) : Highlight nets, registers I don't understand - Ctrl+F , find where they go but that again just confuses me more. I'm clearly approaching this wrong so came here to ask from the experienced people here.
Grateful for any direction.
I have a general question about the use of leading zeros, such as three zeros in "0001", and unnecessary use of parentheses in Verilog.
I know that one can use underscore while wringing numbers for inputs for the purpose of clarity and the underscore is ignore by the compiler. I was just experimenting and notice that leading zeros and unnecessary parentheses are also ignored by the compiler. I'm using Verilogger Extreme.
I wanted to ask if this is universally true with all compilers and if it's okay to do this when one needs to do this for the sake of clarity. Thanks.
Please check the line 57 in the code below. The code compiled okay and the result was correct.
I'm lately coming to understand I suck at testbenching. I always either built basic ones I viewed by eye (maybe output to text), or had ones done for me by verification engeneer.
I want to be able to write complex testbenches, but not to the level of UVM and such, and don't realy want to use python / C for the task.
What I had in mind are components to have driving interfaces easier (nowadays I either write each signal by myself, or use a text to avalon converter somebody wrote in our team, and I'm sure there are better ways to write it than that because it's a horrible piece of code).
I was wondering if there exist a library of different useful testbench 'simple' components (not UVM) I coukd utikize and learn from. Or at least a project with such testbenches of good quality.
I liked vunit approach (and git the idea from them and the uart example), though I don't like being forced to use the vunit python to run tests.
A few months ago I made a post saying that I managed to get Verilator output running on a microcontroller. Last week I had finally managed to make it into something that's ready for the public.
It runs on the Raspberry Pi Pico (or any other RP2040-based board). I'm calling it FakePGA. More details can be found on the project page on Github.
Even though it's many orders of magnitude slower than using a real FPGA, I've managed to get a UART Tx running on it at 4800 baud.
Hi all! I took a FPGA role hackerrank for new grads last Friday, and one question I didn't quite I understand was regarding counting "levels of logic" between 2 variables. Since the test I've searched around for a while but couldn't figure it out, but still want to learn. So thought this community could be my savior!
I've modified the provided code, but the question for both code blocks is: "How many levels of logic are there between input and output?"
module BitSwap ( input logic [3:0] input, output logic [3:0] output ); assign output = input; assign output = input; assign output = input; assign output = input; endmodule
module BitSwapv2 ( input logic clk, input logic [3:0] input, output logic [3:0] output ); always_ff @(posedge clk) begin output <= input | input; output <= input | input; output <= input | input; output <= input | input; end endmodule
Are the levels of logic 0 since no logic gates are used, but just wires are used, for the first block? And the second block has 4 levels of logic since 4 gates are used?
Or perhaps because "logic" is a 4-state data type (0,1,X,Z), the levels of logic between input and output is 4+4=8 for both code blocks?
Thank you so much for everyone's insights!
Edit: fixed RTL bugs pointed out in comments.
EE undergrad here. I am very interested in getting into FPGA design and have been studying some on my own time. I was wondering if it would be better to learn Verilog or VHDL? Which is more widely used, which is easier to pick up, etc. are questions in my mind.
I am writing a HDMI "Hello, world!" text output type of learning project with Verilog, using a Gowin/Sipeed Tang Nano 4K with Gowin FPGA Designer.
However I run into behavior that I find really peculiar, and I am left wondering whether it is me, or if it is actually a Gowin compiler bug (yeah, as if..).
I made a video illustrating the issue, which I posted at https://youtu.be/Q9ZjbK9n3-A . (Be wary, I am no YouTuber), or if you'd just like to look at repro code, it is also available at https://github.com/juj/gowin_array_handling_bug/blob/main/src/top.v .
Thanks for any help - am I doing something wrong?